hanbit h m s2 m 32 m 16g h a n bit el ec troni c s co.,ltd. general description t h e h m s 2 m 32 m 16 g is a high - s p e e d s t a t ic r a ndo m a c c e s s m e m o r y ( s r a m ) m od u l e c on t a ining 2 , 097 , 152 w o r d s o r g a n i z e d i n a x32-b i t c o n f i g u r a t i o n . t h e m o d u l e c o n s i st s o f s i xt e e n 1 m x 4 sr a ms m o u n t e d o n a 72-p i n , d o ub l e -s i d e d , fr4-p r i n t e d c i r cu i t b o a r d . p d 0 t o p d 3 iden t i f y t he m od u le s den s i t y a llowing in t e r c h a nge a b le u s e of a l t e r n a t e den s i t y, ind u s t r y- s t a nd a r d m o d u l e s. f o ur c h i p e n ab l e i n puts, (/ce1, /ce2, /ce3 a n d /ce4) a r e us e d t o e n a b l e t h e m o d u l e s 4 b y t e s inde p enden t ly. o u t pu t en a b le ( / o e ) a nd w r i t e en a b le ( / w e ) c a n s et t he m e m o r y in p u t a nd o u t pu t . d a t a is w r i t t e n in t o t h e s r am m e m o r y wh e n w r i t e e n a b l e ( / w e ) a nd chip e n a b l e ( / c e ) in p u t s a r e b o t h l o w. r e a ding is a c c o m p li s h e d wh e n / w e r e m a ins h i g h a nd / c e a nd o u t pu t e n a b l e ( / o e ) a r e l o w . f or r e li a b ili t y, t his s r am m od u l e is d e s ign e d a s m u l t i p l e p ow e r a nd g r o u nd p in. all m od u l e c o m p on e n t s m a y b e p o w e r e d f r o m a s i n g l e +5 v dc p o w e r supp l y a n d a ll i n puts a n d o utputs a r e fu l l y tt l-c o m p a t i b l e . features ? a cc e ss t i m e s : 10, 12, 15, 17 a n d 20 n s ? h igh - den s i t y 8 m by t e de s ign ? h igh - r e li a b ili t y, high - s p e e d d e s ign ? s ingl e + 5 v 10% p o w e r supp l y ? e a s y m e m o r y e x p a n s ion / c e a nd / o e f u n c t ions ? a ll i n puts a n d o utputs a r e t t l- c o m pat i b l e ? i nd u s t r y - s t a nd a r d p ino u t ? fr4 - pc b d e s i g n ? l o w p r o f il e 72-p i n ? part i d e n t i f i c at i o n - h ms 2 m 3 2 m 1 6 g : s i mm d e s i g n , g o l d l e ad o pti o n s m ar k ing ? t i m i n g 1 0 n s a c c e ss - 1 0 1 2 n s a c c e ss - 1 2 1 5 n s a c c e ss - 1 5 1 7 n s a c c e ss - 1 7 2 0 n s a c c e ss - 2 0 ? pa c k a g e s 7 2 - p i n s i mm m 72- p in s imm to p v iew pin assign m ent nc nc pd2 pd3 vss pd0 pd1 d q 0 d q 8 d q 1 d q 9 d q 2 d q 10 d q 3 d q 11 vcc a0 a7 a1 a8 a2 a9 d q 12 d q 4 d q 13 d q 5 d q 14 d q 6 d q 15 d q 7 vss / w e a15 a14 /c e 2 /c e 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 /c e 4 /c e 3 a17 a16 /oe vss d q 24 d q 16 d q 25 d q 17 d q 26 d q 18 d q 27 d q 19 a3 a10 a4 a11 a5 a12 vcc a13 a6 d q 20 d q 28 d q 21 d q 29 d q 22 d q 30 d q 23 d q 31 vss a18 a19 a20 nc 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 sram modu l e 8mbyt e (2m x 32-bit) p a r t n o. h m s 2 m 32 m 16g h a n b i t
hanbit hms2m32m16g hanbit electronics co.,ltd. functional block diagram a0-a19 / we u2 dq4-7 / oe /ce a0-a19 / we u1 dq0-3 / oe /ce dq0 C dq31 a0 C a19 / ce01 / ce02 / ce03 / ce04 / oe / we / ce11 / ce12 / ce13 / ce14 a0-a19 / we u3 dq8-11 / oe /ce a0-a19 / we u10 dq4-7 / oe /ce a0-a19 / we u4 dq12-15 / oe /ce a0-a19 / we u7 dq24-27 / oe /ce a0-a19 / we u6 dq20-23 / oe /ce a-a19 / we u5 dq16-19 / oe /ce a0-a19 / we u11 dq8-11 / oe /ce a0-a19 / we u12 dq12-15 / oe /ce a0-a19 / we u13 dq16-19 / oe /ce a0-a19 / we u14 dq20-23 / oe /ce a0-a19 / we u15 dq24-27 / oe /ce a0-a19 / we u16 dq28-31 / oe /ce a0-a19 / we u8 dq28-31 / oe /ce a0-a19 / we u9 dq0-3 / oe /ce
hanbit hms2m32m16g hanbit electronics co.,ltd. truth table mode /oe /ce /we output power standby x h x high-z standby not selected h l h high-z active read l l h d out active write x l l d in active 74f04 74f32 74f32 74f32 74f32 74f32 74f32 74f32 74f32 a(20) / ce1 / ce2 / ce3 / ce4 / lce1 / hce1 / lce2 / hce2 / lce3 / hce3 / lce4 / hce4
hanbit hms2m32m16g hanbit electronics co.,ltd. absolute maximum ratings parameter symbol rating voltage on any pin relative to vss v in,out -0.5v to +7.0v voltage on vcc supply relative to vss v cc -0.5v to +7.0v power dissipation p d 16w storage temperature t stg -65 o c to +150 o c operating temperature t a 0 o c to +70 o c ? stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions a bove those indicated in the operating section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions ( t a =0 to 70 o c ) parameter symbol min typ. max supply voltage v cc 4.5v 5.0v 5.5v ground v ss 00 0 input high voltage v ih 2.2 - vcc+0.5v** input low voltage v il -0.5* - 0.8v * v il (min.) = -2.0v ac (pulse width 10ns) for i 20 ma ** v ih (min.) = vcc+2.0v ac (pulse width 10ns) for i 20 ma dc and operating characteristics (1) (0 o c t a 70 o c ; vcc = 5v 0.5v ) parameter test conditions symbo l min max units input leakage current v in =vss =vcc il i -2 2 m a output leakage current /ce=v ih or / oe =v ih or /we=v il v out =vss to v cc il 0 -2 2 m a output high voltage i oh = -4.0ma v oh 2.4 v output low voltage i ol = 8.0ma v ol 0.4 v * vcc=5.0v, temp=25 o c dc and operating characteristics (2) max description test conditions symbol -10 -12 -15 unit power supply current: operating min. cycle, 100% duty /ce=v il , v in =v ih or v il , i out =0ma l cc 195 190 185 ma min. cycle, /ce=v ih l sb 50 50 50 ma power supply current :standby f=0mhz, /ce 3 v cc -0.2v, v in 3 v cc -0.2v or v in 0.2v l sb1 10 10 10 ma
hanbit hms2m32m16g hanbit electronics co.,ltd. capacitance description test conditions symbol max unit input /output capacitance v i/o =0v c i/o 8pf input capacitance v in =0v c in 7pf * note : capacitance is sampled and not 100% tested ac characteristics (0 o c t a 70 o c ; vcc = 5v 0.5v, unless otherwise specified) test conditions parameter value input pulse level 0 to 3v input rise and fall time 3ns input and output timing reference levels 1.5v output load see below read cycle -10 -12 -15 parameter symbol min max min max min max unit read cycle time t rc 10 - 12 - 15 - ns address access time t aa -10 - 12 - 15 ns chip select to output t co -10 - 12 - 15 ns output enable to output t oe -5-6-7ns chip enable to low-z output t lz 3-3-3-ns output enable to low-z output t olz 0-0-0-ns output disable to high-z output t ohz 050607ns chip disable to high-z output t hz 050607ns output hold from address change t oh 3-3-3-ns chip select to power up time t pu 0-0-0-ns chip select to power down time t pd -10 12 - 15 ns +5.0v 480 w 255 w 5pf* d out output load (b) for t hz , t lz , t whz , t ow , t olz & t ohz v l =1.5v 50 w 30pf d out z0=50 w output load (a)
hanbit hms2m32m16g hanbit electronics co.,ltd. write cycle -10 -12 -15 parameter symbol min max min max min max unit write cycle time t wc 10 - 12 - 15 - ns chip select to end of write t cw 7-8-10-ns address set-up time t as 0-0-0-ns address valid to end of write t aw 7-8-10-ns write pulse width (/oe high) t wp 7-8-10-ns write recovery time t wr 0-0-0-ns write to output high-z t whz 050607ns data to write time overlap t dw 5-6-7-ns data hold from write time t dh 0-0-0-ns end of write to output low-z t ow 3-3-3-ns timing diagrams timing waveform of read cycle ( address controlled)( /ce =/oe = v il , /we = v ih ) t rc address data out previous data valid data valid t oh t aa
hanbit hms2m32m16g hanbit electronics co.,ltd. data valid data valid timing waveform of read cycle ( /we = v ih ) notes (read cycle) 1. /we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load (b). this parameter is sampled and not 100% tested. 6. device is continuously selected with /ce = v il . 7. address valid prior to coincident with /ce transition low. timing waveform of write cycle (/oe = clock ) t aa t co t lz(4,5 ) high-z l sb 50% 50% t pd address /ce /oe data out vcc supply current t rc t pu l cc t oe t olz t oh t ohz t hz ( 3,4,5 ) t wc address /oe /ce /we data in data out t aw t wr(5) t cw(3) t as(4) t wp(2) t dw t dh high-z t ohz t ow high-z
hanbit hms2m32m16g hanbit electronics co.,ltd. data valid timing waveform of write cycle (/oe low fixed) notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low /ce and a low /we. a write begins at the latest transition among /ce going low and /we going low: a write ends at the earliest transition among /ce going high and /we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of /ce going low to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as /ce, or /we going high. 6. if /oe,/ce and /we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is n ecessary during read and write cycle. 8. if /ce goes low simultaneously with /we going low or after /we going low, the outputs remain high impedance state. 9. d out is the read data of the new address. 10. when /ce is low: i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. functional description /ce /we /oe mode i/o pin supply current h x* x not select high-z i sb , i sb1 l h h output disable high-z i cc lhl read d out i cc l l x write d in i cc note: x means don't t aw t cw(3) t wr(5) t as(4) t wp(2) t oh t dw t dh t whz(6,7) high-z high-z(8) t ow (10) (9) t wc address /ce /we data in data out
hanbit hms2m32m16g hanbit electronics co.,ltd. package dimmensions simm design (solder & gold plating lead) 0.25 mm max min 2.54 mm 1.27 gold: 1.04 0.10 mm solder: 0.914 0.10 mm 1 72 107.95 mm 2.0 mm 1.02 mm 6.35 mm 1.27 mm 95.25 mm 10.16 mm 10.16 mm .125 (3.18) t yp(2x) 3.38 mm 6.35 mm 6.35 mm 3.38 mm 27.0 mm 1.29 0.08mm
hanbit hms2m32m16g hanbit electronics co.,ltd. ordering information 1. - product line identifier hanbit ------------------------------------------------------- h 2. - memory modules 3. - sram 4. - depth : 2m 5. - width : x 32bit 6. - package code simm ------------------------------------------------------- m 7. - number of memory components C16, lead finish gold -- g 8. - access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns sram x32bit 1 2 3 4 5 6 7 8 15ns access time h m s 2m 32 m 16g - 15 hanbit memory modules simm 2m component, gold
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